A conventional memory circuit 1 including a memory cell 2 is shown in FIG. 1. The illustrated memory circuit 1 performs programming of the memory cell 2 including programming the memory cell to set and reset memory states. In particular, a transistor 3 applies signals to the memory cell 2 to program the memory cell 2 to the different memory states. For example, a voltage potential may be applied to the memory cell 2 to program the memory cell 2 from a set to a reset state.
Referring to FIG. 2, a graphical representation of cell current and cell voltage (Vcell) is shown. In addition, curves of the memory cell 2 in a low electrical resistance state (LRS) and a high electrical resistance state (HRS) are also shown. A plurality of operation points 6, 7 are provided at intersections of a load line 5 of the circuitry of FIG. 1 with the LRS and HRS curves of the memory cell. During an example programming operation, the memory cell 2 changes from the low electrical resistance state to the high electrical resistance state.
However, as shown in FIG. 2, if the current or voltage is initially controlled at the beginning of the programming between the low to high resistance states, then the current or voltage is at operation point 7 when the cell 2 is in the high resistance state and which may not be controlled. Likewise, if the current or voltage is controlled when the cell 2 is in the high resistance state, then the current or voltage is at operation point 6 when the cell 2 is in the low resistance state and which may not be controlled.
At least some embodiments are directed towards memories, memory systems and memory programming methods which provide increased flexibility of memory cell programming compared with some conventional arrangements.